Integrated Circuit (IC) technology has advanced greatly over the past fifty years. ICs are now pervasive and present in electronic devices, machinery, vehicles, appliances, and many other devices. Large processing ICs now include billions of transistors while memory ICs include hundreds of billions of transistors. The density of transistors on ICs can reach 100 million transistors per square millimeter.
Transistors of the ICs are formed in a semi conducive portion of the IC and are interconnected by patterned conductors formed in ten or more metal layers of the IC. Such interconnection of the transistors creates logic functions. The metal layers are also used to route signals within the IC, to route signals external to the IC, and to distribute supply voltages to the transistors, e.g., source supply voltage (VSS) and drain supply voltage (VDD), often referred to as power and ground, respectively. Distribution of VSS and VDD within an IC uses patterned conductors formed in one or more metal layers and vias that intercouple the metal layers. Because of dimensional constraints in the metal layers, the patterned conductors may have relatively high serial resistance. The flow of current through these patterned conductors therefore results in IR drop (voltage drop) which lowers voltage applied to transistors reducing circuit performance and generating heat during power delivery. While the voltage drop reduces the performance of the IC, generated heat must be dissipated to avoid destruction of the IC. The IR drop at edges of power domains may be greater because of the longer conductor lengths servicing transistors at the boundaries of the power domains.
FIG. 1A is a diagram illustrating a pattern of package pads of a prior flip chip package. The package pads of the package are electrical connections, e.g., conductive pads, that correspond directly to and electrically connect with the electrical connections of the IC. The package also includes a secondary interface, e.g., Printed Circuit Board (PCB) interface. The PCB interface includes electrical connections, e.g., solder balls, that correspond directly to the electrical connections on a PCB upon which the package mounts.
As shown in FIG. 1A, the flip chip package 100 includes a plurality of I/O pads 102 for connecting to I/O connections of an IC and a plurality of internal power/ground pads 104 for connecting to VSS and VDD connections of the IC. Current flip chip packaging technology supports lateral separation pitches between I/O pads 102 down to 60 microns and lateral separation pitches between interposers down to 40 microns. However, current flip chip packaging technology only supports lateral separation pitches between internal power/ground pads 104 down to 200 microns. Because of this, VSS and VDD must be laterally distributed within the IC as described above, causing the problems discussed. The terms “lateral separation pitch” and “pitch” are used interchangeably herein.
FIG. 1B is a sectional side view illustrating a portion of a prior packaged IC 150. Fiber glass core 162 is used as a basis for the IC package. Vias 174 and 188 are formed in the core 162 via laser drilling and filling with a conductive material, e.g., copper. Patterned conductors 172, 176, 187 and 190 are formed on the core 162. Dielectric layers 160 and 164 are formed on the core 162 to insulate the patterned conductors 172, 176, 187 and 190. Next, holes are laser drilled in the dielectric layers 160 and 164 and vias 170, 186, 177 and 191 are formed therein to couple to patterned conductors 172, 187, 176 and 190, respectively. Dielectric layers 158 and 166 insulate patterned conductors 168, 178, 184, and 192. Package pads 180 and 194 include bumps (e.g., solder bumps or Cu pads) and conductive vias that extend through dielectric layer 166 to patterned conductors 178 and 192. An IC 156 includes IC pads 182 and 196 that electrically couple to package pads 180 and 194, respectively. Printed Circuit Board (PCB) pads 152 and 154 electrically couple to conductors 168 and 184, respectively, through dielectric layer 158. The PCB pads may be solder balls. The packaged IC 150 may be mounted on a PCB (not shown) with the PCB pads 152 and 154 electrically coupling the packaged IC 150 to the PCB.
The laser drilling techniques used to construct the prior IC package of FIGS. 1A and 1B limit dimensions of vias to a minimum diameter of approximately 50-60 microns. The position accuracy of the laser drill is about 30 microns. Therefore, the minimum via pad size is limited to approximately 110 to 120 microns. Dimensions of the patterned conductors are limited by the dimensions of the via pad. Thus, prior IC packages typically had lateral separation pitch between internal power/ground package pads of 200 microns, and a minimum of 150 microns. Such construct resulted in the distribution of power and ground within the IC greater than 200 microns from the bumps, generating heat and voltage degradation. Further, dielectric layers of IC packages upon which the package pads were formed were typically not perfectly planar, which put stress on the ICs in response to being mounted to the IC packages. What is needed, therefore, is an improved IC package with reduced lateral separation pitches between power/ground pads.